Many types of power switching circuit using insulated gate transistors have been proposed. There are several types of insulated gate transistors (electrostatic induction-type self-arc-suppressing elements), e.g. an insulated gate bipolar transistor (hereinafter referred to as IGBT) has an insulated gate and it is operated in a bipolar mode, and an insulated gate field effect transistor (Metal Oxide Semiconductor field effect transistor) has an insulated gate and it is operated in a field effect mode.
Because of the compactness and low-noise performance of power supplies, the insulated gate transistor which makes possible high-speed switching has been widely used in recent years. In IGBT, for example, the collector current is determined based on the gate and collector voltages as shown in FIG. 5. When the insulated gate transistors are used as the main switch of inverters for high-speed switching operations, the following problems exist: When an arm or load short-circuit of the inverter power supply occurs, the insulated gate transistors with on-state share most of the parts of power supply. As a result, by the relationship shown in FIG. 5, an extremely large short-circuit current flows. In the case of IGBT, as described in the Japanese laid-open patent application no. 61-185064, as the collector current increases greatly, these insulated gate transistors are destroyed by latch-up phenomenon originating from the out-of control gate voltage. However, in many cases, by cutting large current through high speed operations, transitional voltage greatly increases by energy from the circuit inductance at the breaking instance, thereby destroying the insulated gate transistors.
Therefore, there have been proposals for an insulated gate transistor to control the gate voltage (Japanese laid-open patent application no. 61-147736, Japanese laid-open patent application no. 61-185064, Japanese laid-open patent application no. 61-251323, Japanese laid-open patent application no. 62-277063, Japanese laid-open patent application no. 63-95722, Japanese laid-open patent application no. 63-95728, U.S. Pat. No. 4,581,540 and U.S. Pat. No. 4,721,869). These are methods which reduce the overcurrent to break it and are preferable in that the overcurrent is detected and reduced to be broken during the ON state of the insulated gate transistor.
However, in an inverter apparatus and so forth which carries out a high speed switching operation, there is a problem in that even if the overcurrent is detected, the ON state of the insulated gate transistor is finished by the input signal while reducing the overcurrent, and the insulated gate transistor is destroyed by transitional voltage, which is caused by breaking the overcurrent at the end, since the ON state of the insulated gate transistor is short.
Furthermore, these conventional methods are suitable for general application because the collector current can be reduced by suppressing the gate voltage, based on the overcurrent of the insulated gate transistor which is detected from an increase in collector voltage.
It was difficult to determine whether a short-circuit accident occurs or not unless it is determined whether the high collector to emitter voltage is caused by either overcurrent or transient phenomena, since the turn-on operation has a delay in relation to the gate voltage. Therefore, in the conventional circuits, e.g. U.S. Pat. No. 4,721,869, when an abnormality is detected by the detecting circuit, an adjusting circuit performs a dropping operation of the gate voltage of the IGBT immediately after the passage of a predetermined time following the application of the ON signal to the gate.
However, when high speed switching operations are required as in inverter apparatus, the conduction period of the insulated gate transistor for one time is short. Therefore, the predetermined time is relatively long compared with the conducting period and, eventually, the probability that the overcurrent cannot be detected increases.